This invention relates to microprocessor architecture adapted for efficient operation on single-precision, multiple-precision and floating-point data.
Digital signal processors are widely used in modern systems of all types. Where processing must be accomplished on data having different numbers of bits, as for example 8, 16, or 32-bit data paths, difficulties arise in configuring the architecture to efficiently accommodate the various types of data. For example, where 8, 16, and 32-bit data is to be processed, and a portion of the data may be in floating-point form with a 24-bit mantissa and an 8-bit exponent, it is possible to use a 16-bit arithmetic logic unit (ALU) to operate on 16 bits of the data on each clock cycle, temporarily storing the carry bits until the next operating cycle. The problem with using a 16-bit microprocessor to perform 32-bit operations is that multiple clock cycles are required, thereby slowing the overall operation. The 16-bit ALU, when required to handle 8-bit data, requires preprocessing of the 8 bits to configure it to the 16-bit processing path or format. When a 24-bit mantissa together with an 8-bit exponent are to be processed, the situation using the 16-bit ALU is even worse, because the 24-bit mantissa portion of the data must be broken into two portions, thereby requiring at least two clock cycles, followed by a further clock cycle operating on the exponent.
One can use a 32-bit processor or ALU to process 32-bit signals. This has the advantage that 32 bits can be processed in a single clock cycle on each pass. However, the 32-bit ALU microprocessor requires preprocessing in order to handle both 16-bit and 8-bit signals. The 24-bit mantissa with 8-bit exponent further requires independent processing of the mantissa and exponent portions, by "unpacking", and further requires preprocessing of the mantissa portion. The preprocessing, unpacking and the like may undesirably require additional hardware, additional clock cycles, or both.
Where multiple data types such as 8, 16, and 32-bit as described above are to be handled, and the data increments are capable of being packed into groupings smaller than the largest grouping, as for example, by using a 16-bit ALU system, a further problem occurs in that successive 16-bit words representing MSB and LSB portions of a single 32-bit word must be loaded into appropriate portions of the ALU for correct processing. An ALU arrangement capable of efficiently handling various data types is desirable.